Recognition method for photolithography process and semiconductor device

ABSTRACT

A recognition method for photolithography process and a semiconductor device are provided. The recognition method includes forming a mask layer on a semiconductor substrate, and then patterning the mask layer to form multiple dense line patterns in a cell region and multiple dummy dense line patterns in an interface region between the cell region and a peripheral region. At least one connection portion is provided between a first and a third dummy dense line patterns, and a second dummy dense line pattern is discontinuous at and separated from the at least one connection portion. A photoresist layer covering the peripheral region is formed on the semiconductor substrate, and whether a landing position of the photoresist layer is correct is determined according to a distance from an edge of the photoresist layer to a closest dummy dense line pattern and a width of the at least one connection portion.

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of Taiwan applicationserial no. 109119926, filed on Jun. 12, 2020. The entirety of theabovementioned patent application is hereby incorporated by referenceherein and made a part of this specification.

BACKGROUND Technical Field

This disclosure relates to a semiconductor process technology, and inparticular to a recognition method for a photolithography process and asemiconductor device.

Description of Related Art

Lithography is a pivotal technology in a semiconductor devicemanufacturing process, and is a step that determines everything relatedto a metal oxide semiconductor device structure, for example, patternsof each film layer and doped regions. In general, a lithography processincludes photoresist coating, exposure and development. In the exposurestep, a light source irradiates a photoresist via a photomask to cause aphotochemical change in an exposure region of the photoresist. Then, bybaking and development, a photomask pattern can be transferred to thephotoresist and a patterned photoresist layer is formed.

As the density of integrated circuits increases, the size (line width)of the entire semiconductor device decreases. Therefore, in response tothe miniaturization of the device, a self-aligned double patterning(SADP) process has been developed to overcome the limitations of currentphotolithography processes, in which a line/space ratio can be reducedto the nanometer scale, thereby miniaturizing the device.

However, in the SADP process, since a dense line mask formed on asemiconductor substrate usually has constant line width and line space,it is difficult to distinguish between different patterns generated(i.e., perform core-gap recognition), and it is also not easy todetermine a boundary between a cell region and a peripheral region. As aresult, a landing position of the subsequent patterned photoresist layeris affected.

In addition, since the landing position (edge) of the patternedphotoresist layer is set at the design stage of the device, there hasbeen a huge demand for a method capable of online recognizing whetherthe landing position of the photoresist layer is correct.

SUMMARY

The disclosure provides a recognition method for a photolithographyprocess, which directly determines a boundary between a cell region anda peripheral region, and online recognizes whether a landing position ofa photoresist layer is correct.

The disclosure provides a semiconductor device, which is a semiconductordevice with a specific structure fabricated by the abovementionedrecognition method.

The recognition method for a photolithography process of the disclosureincludes the following steps. A mask layer is formed on a semiconductorsubstrate that includes a cell region and a peripheral region. The masklayer is patterned to form multiple dense line patterns in the cellregion and multiple dummy dense line patterns in an interface regionbetween the cell region and the peripheral region. At least oneconnection portion is provided between a first and a third of themultiple dummy dense line patterns. A second of the multiple dummy denseline patterns is discontinuous at the at least one connection portionand separated from the at least one connection portion. A photoresistlayer covering the peripheral region is formed on the semiconductorsubstrate. Whether a landing position of the photoresist layer iscorrect is determined according to a distance from an edge of thephotoresist layer to a closest one of the multiple dummy dense linepatterns and a width of the at least one connection portion.

In an embodiment of the disclosure, in a case where the photoresistlayer is set to cover the first of the multiple dummy dense linepatterns, the landing position of the photoresist layer is determined tobe incorrect in response to the distance from the edge of thephotoresist layer to the closest one of the multiple dummy dense linepatterns being smaller than a distance between the first and the secondof the multiple dummy dense line patterns.

In an embodiment of the disclosure, in a case where the photoresistlayer is set to cover the first of the multiple dummy dense linepatterns, the landing position of the photoresist layer is determined tobe incorrect in response to a measured value being unable to be obtainedby a critical dimension scanning electron microscope (CD-SEM).

In an embodiment of the disclosure, in a case where the photoresistlayer is set to cover the second of the multiple dummy dense linepatterns, the landing position of the photoresist layer is determined tobe incorrect in response to the distance from the edge of thephotoresist layer to the closest one of the multiple dummy dense linepatterns being smaller than the distance between the first and thesecond of the multiple dummy dense line patterns.

In an embodiment of the disclosure, in a case where the photoresistlayer is set to cover the second of the multiple dummy dense linepatterns, the landing position of the photoresist layer is determined tobe incorrect in response to a measured value being unable to be obtainedby a CD-SEM.

In an embodiment of the disclosure, the recognition method may furtherinclude the following. A critical dimension (CD) value of thephotoresist layer is estimated according to a value of the distancebetween opposite sides (from the edge of the photoresist layer to theclosest one of the multiple dummy dense line patterns).

In an embodiment of the disclosure, the recognition method may furtherinclude the following. An overlap amount is measured according to adifference in the distance between opposite sides (from the edge of thephotoresist layer to the closest one of the dummy dense line pattern).

In an embodiment of the disclosure, a method for patterning the masklayer includes a self-aligned double patterning (SADP) process.

The semiconductor device of the disclosure includes a semiconductorsubstrate that includes a cell region and a peripheral region, multipledense line structures and a truncating circuit. The multiple dense linestructures are formed in or on the semiconductor substrate.

The multiple dense line structures are obtained by carrying out anetching process or a deposition process using the multiple dense linepatterns in the abovementioned recognition method as a mask, and themultiple dense line structures and the multiple dense line patterns arecomplementary patterns. The truncating circuit is disposed on aninterface between the multiple dense line structures and the peripheralregion. The truncating circuit is obtained by carrying out an etchingprocess or a deposition process using the photoresist layer and themultiple dummy dense line patterns in the abovementioned recognitionmethod as a mask. The truncating circuit and the first to the third ofthe multiple dummy dense line patterns are complementary patterns, andthe truncating circuit has at least one truncating portion complementaryto the at least one connection portion of the dummy dense line patterns.

In another embodiment of the disclosure, the multiple dense linestructures include a buried word line (BWL), a bit line (BL), or ashallow trench isolation (STI) structure.

In another embodiment of the disclosure, a line width of the truncatingcircuit is equal to a line width of the multiple dense line structures.

In another embodiment of the disclosure, the truncating circuit includesmultiple extensions adjacent to the at least one truncating portion andextending toward the peripheral region.

In another embodiment of the disclosure, the truncating circuit isconstituted by multiple closed rings, and the at least one truncatingportion is disposed between two of the multiple closed rings.

In another embodiment of the disclosure, a line width of each of themultiple closed rings is equal to a line width of the multiple denseline structures.

Based on the above, in the disclosure, a photolithography process iscarried out using a mask layer with a specific pattern, in which notonly can the boundary between the cell region and the peripheral regionbe directly determined, but it can also be online recognized whether thelanding position of the photoresist layer is correct. In addition, theabovementioned recognition method may also be applied to detection ofcritical dimension (CD) and overlap.

To make the disclosure more comprehensible, several embodimentsaccompanied by drawings are described in detail as follows.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1A, 2A, 3A, 4A, 5A, and 6A are schematic top views of amanufacturing process of a recognition method for a photolithographyprocess according to a first embodiment of the disclosure.

FIGS. 1B, 2B, 3B, 4B, 5B, and 6B are respectively schematiccross-sectional views of FIGS. 1A, 2A, 3A, 4A, 5A, and 6A taken alongline X-X′.

FIGS. 1C, 2C, 3C, 4C, 5C, and 6C are respectively schematiccross-sectional views of FIGS. 1A, 2A, 3A, 4A, 5A, and 6A taken alongline Y-Y′.

FIG. 7A is a schematic top view of a semiconductor device according to asecond embodiment of the disclosure.

FIG. 7B is a schematic cross-sectional view of FIG. 7A taken along theline X-X′.

FIG. 7C is a schematic cross-sectional view of FIG. 7A taken along theline Y-Y′.

FIG. 8A is a schematic top view of a recognition method for aphotolithography process according to a third embodiment of thedisclosure.

FIG. 8B is a schematic cross-sectional view of FIG. 8A taken along theline X-X′.

FIG. 8C is a schematic cross-sectional view of FIG. 8A taken along theline Y-Y′.

FIG. 9 is a schematic top view of a semiconductor device according to afourth embodiment of the disclosure.

FIG. 10A is a top view of the first embodiment applied to criticaldimension (CD) detection.

FIG. 10B is a top view of the first embodiment applied to overlapdetection.

DESCRIPTION OF THE EMBODIMENTS

FIGS. 1A, 2A, 3A, 4A, 5A, and 6A are schematic top views of amanufacturing process of a recognition method for a photolithographyprocess according to a first embodiment of the disclosure. FIGS. 1B, 2B,3B, 4B, 5B, and 6B are respectively schematic cross-sectional views ofFIGS. 1A, 2A, 3A, 4A, 5A, and 6A taken along the line X-X′. FIGS. 1C,2C, 3C, 4C, 5C, and 6C are respectively schematic cross-sectional viewsof FIG. 1A, 2A, 3A, 4A, 5A, and 6A taken along the line Y-Y′.

With reference to FIGS. 1A, 1B, and 1C, a mask layer 102 is formed on asemiconductor substrate 100 that includes a cell region 10 a and aperipheral region 10 b. The semiconductor substrate 100 may be formed ofat least one semiconductor material selected from the group consistingof silicon (Si), germanium (Ge), silicon-germanium (SiGe), galliumphosphide (GaP), gallium arsenide (GaAs), silicon carbide (SiC),silicon-germanium-carbon (SiGeC), indium arsenide (InAs), and indiumphosphide (InP). In addition, although not illustrated, in anembodiment, a device isolation structure (such as a shallow trenchisolation (STI) structure), a doped region (such as a well region), etc.may be formed in the semiconductor substrate 100. The mask layer 102 maybe constituted by material layers 102 a, 102 b, 102 c, 102 d, 102 e, 102f, 102 g, and 102 h with different etch selectivities. For example,adjacent material layers are different from each other, and non-adjacentmaterial layers may be the same or different. In an embodiment, thematerial layers 102 a to 102 h from bottom to top are respectively madeof, for example, plasma enhanced tetraethyl orthosilicate (PE-TEOS)silicon oxide, diamond-like carbon (DLC), nitrogen-rich siliconoxynitride (N-SiON), silicon-rich silicon oxynitride (Si-SiON), DLC,oxygen-rich silicon oxynitride (O-SiON), spin-on carbon (SOC) and aspin-on self-assembly (SOSA) material. However, the disclosure is notlimited thereto. The selection and arrangement of the aforementionedmaterials may be changed according to requirements, some of the materiallayers may be omitted, or other material layers may be added to thematerial layers 102 a to 102 h. After that, in order to pattern the masklayer 102, a method such as a self-aligned double patterning (SADP)process may be used, where the material layers 102 g and 102 h are firstpatterned by photolithography to form multiple line patterns 104. At thesame time, a connection block 106 is formed between a first and a secondline patterns 104 adjacent to an interface between the cell region 10 aand the peripheral region 10 b.

Next, with reference to FIGS. 2A, 2B, and 2C, a spacer 108 is formed oneach of sidewalls of the line patterns 104 and the connection block 106.The formation method of the spacer 108 includes, for example, depositinga material of the spacer 108 conformally on each of the line patterns104 and the connection block 106, and etching back this material untilthe material layer 102 f is exposed. The material of the spacer 108includes, for example, silicon oxide or other suitable materials.

Then, with reference to FIGS. 3A, 3B, and 3C, after removal of the linepatterns and the connection block (that is, 104 and 106 in the precedingfigures), the spacer (that is, 108 in the preceding figures) is used asan etching mask to transfer its pattern to the exposed material layer(that is, 102 f in the preceding figures). The patterned material layeris then used as an etching mask to transfer its pattern to the materiallayer (that is, 102 e in the preceding figures) underneath, and apatterned material layer 102 e′ is formed and the material layer 102 dis exposed. The material layer above the patterned material layer 102 e′may also be removed after this step.

Thereafter, with reference to FIGS. 4A, 4B and 4C, an oxide layer 110 isdeposited on the semiconductor substrate 100, and the oxide layer 110 isetched back to expose the top of the patterned material layer 102 e′.

Next, with reference to FIGS. 5A, 5B and 5C, after removal of thepatterned material layer (that is, 102 e′ in the preceding figures), theoxide layer 110 is used as an etching mask to transfer its pattern tothe exposed material layer (that is, 102 d in the preceding figures),and a patterned material layer 102 d′ is formed and the material layer102 c is exposed.

The oxide layer 110 and the patterned material layer 102 d′ at thisstage may be regarded as a mask layer after patterning, because thematerial layers 102 a to 102 c below maintain the same pattern in thecell region 10 a in subsequent processes. The oxide layer 110 and thepatterned material layer 102 d′ in the cell region 10 a constitutemultiple dense line patterns 112, while multiple dummy dense linepatterns 114 are distributed in an interface region between the cellregion 10 a and the peripheral region 10 b. The dummy dense linepatterns 114 are also distributed in the peripheral region 10 b. Here,the term “dummy” is used to describe a structure to be removed in asubsequent substitution process or a functionless structure. At leastone connection portion 116 is provided between a first dummy dense linepattern 114 ₁ and a third dummy dense line pattern 114 ₃, and a seconddummy dense line pattern 114 ₂ is discontinuous at the connectionportion 116 and separated from the connection portion 116.

Then, with reference to FIGS. 6A, 6B, and 6C, a photoresist layer 118covering the peripheral region 10 b is formed on the semiconductorsubstrate 100. For clarity, the markings X-X′ and Y-Y′ are omitted inFIG. 6A. Due to the presence of the connection portion 116, a boundarybetween the cell region 10 a and the peripheral region 10 b may bedetermined directly according to visual observation (such as by anoptical microscopy (OM) or scanning electron microscopy (SEM) image).After that, whether a landing position of the photoresist layer 118 iscorrect may be determined according to a distance d1 from an edge 118 aof the photoresist layer 118 to the dummy dense line pattern 114 ₂ thatis closest to the edge 118 a and a width w of the connection portion116. Here, the “width” of the connection portion 116 refers to adimension of the connection portion 116 parallel to an extensiondirection of the dummy dense line patterns 114.

In detail, in a case where the photoresist layer 118 is set to cover thethird dummy dense line pattern 114 ₃, if the distance dl from the edge118 a of the photoresist layer 118 to the closest dummy dense linepattern 114 ₂ is smaller than a distance d2 between the third dummydense line pattern 114 ₃ and the second dummy dense line pattern 114 ₂,it is determined that the landing position of the photoresist layer 118is incorrect. In a case where the edge 118 a of the photoresist layer118 is set to land precisely in the center of the third dummy dense linepattern 114 ₃, if the distance dl from the edge 118 a of the photoresistlayer 118 to the closest dummy dense line pattern 114 ₂ is not equal toa sum of the distance d2 and half of a line width of the third dummydense line pattern 114 ₃, it is determined that the landing position ofthe photoresist layer 118 is incorrect. However, the disclosure is notlimited thereto, and tolerances are allowed in the above settings.

In addition, even if the edge 118 a of the photoresist layer 118 isshifted onto the second dummy dense line pattern 114 ₂, there is apossibility that the distance dl may still meet the aforementionedspecification value. Therefore, it is necessary to perform a doublecheck by measuring the width w of the connection portion 116. Aninstrument such as a critical dimension scanning electron microscope(CD-SEM) is generally used to measure a set landing position. As shownin FIG. 6A, the measurement of the width w is performed on a portion ata fixed spacing apart from the edge 118 a. Thus, when the edge 118 a isshifted onto the second dummy dense line pattern 114 ₂, the instrumentis unable to obtain a measured value and the landing position of thephotoresist layer 118 is determined to be incorrect.

In another embodiment, in a case where the photoresist layer 118 is setto cover the second dummy dense line pattern 114 ₂, if a distance fromthe edge 118 a of the photoresist layer 118 to the dummy dense linepattern 114 ₁ that is closest to the edge 118 a is smaller than adistance between the first dummy dense line pattern 114 ₁ and the seconddummy dense line pattern 114 ₂, the landing position of the photoresistlayer 118 is determined to be incorrect. Even if the determinationresult is positive, it is necessary to measure the width w of theconnection portion 116 by the CD-SEM. If a measured value cannot beobtained, it is determined that the landing position of the photoresistlayer 118 is incorrect, and so on.

FIG. 7A is a schematic top view of a semiconductor device according to asecond embodiment of the disclosure. FIG. 7B is a schematiccross-sectional view of FIG. 7A taken along the line X-X′. FIG. 7C is aschematic cross-sectional view of FIG. 7A taken along the line Y-Y′.Moreover, in the second embodiment, the same reference numerals as thoseof the first embodiment denote the same components and reference may bemade to the foregoing descriptions. Therefore, the same technicalcontent is omitted.

With reference to FIGS. 7A, 7B, and 7C, a semiconductor device 700 ofthe second embodiment includes the semiconductor substrate 100 thatincludes the cell region 10 a and the peripheral region 10 b, multipledense line structures 702 and a truncating circuit 704. Thesemiconductor device 700 uses the photoresist layer 118, the dummy denseline patterns 114 and the dense line patterns 112 of FIG. 6A as a maskto carry out a series of etching processes as follows. First, a trench706 is formed in the semiconductor substrate 100. Then, the materiallayers above the material layer 102 a are removed, and a conductormaterial is filled. Therefore, the dense line structures 702 and thedense line patterns 112 of FIG. 6A are complementary patterns. Thetruncating circuit 704 is disposed on an interface between the denseline structures 702 and the peripheral region 10 b. As described above,the truncating circuit 704 uses the photoresist layer 118 and the dummydense line patterns 114 of FIG. 6A as a mask. Therefore, the truncatingcircuit 704 and the first dummy dense line pattern 114 ₁ to the thirddummy dense line pattern 114 ₃ of FIG. 6A are complementary patterns,and the truncating circuit 704 has at least one truncating portion 708complementary to the connection portion 116 of FIG. 6A. In FIG. 7A, thetruncating circuit 704 is constituted by two closed rings, thetruncating portion 708 is disposed between the two closed rings, and aline width of each closed ring may be equal to or not equal to a linewidth of the dense line structures 702. In the embodiment, the denseline structures 702 are, for example, buried word lines (BWL). However,the disclosure is not limited thereto, and the dense line structures 702may also be shallow trench isolation (STI) structures or bit lines (BL).If the dense line structures 702 are STI structures, the trench 706 isfilled with an insulating material; if the dense line structures 702 areBL, the trench 706 may not be formed, and a deposition process may bedirectly carried out on the semiconductor substrate 100.

FIG. 8A is a schematic top view of a recognition method for aphotolithography process according to a third embodiment of thedisclosure. FIG. 8B is a schematic cross-sectional view of FIG. 8A takenalong the line X-X′. FIG. 8C is a schematic cross-sectional view of FIG.8A taken along the line Y-Y′. Moreover, reference may be made to thefront-end process (as shown in FIGS. 1A to 5C) of the first embodimentfor the manufacturing process of the third embodiment. In the thirdembodiment, the same reference numerals as those of the first embodimentdenote the same components, and reference may be made to the foregoingdescriptions. Therefore, the same technical content is omitted.

With reference to FIGS. 8A, 8B and 8C, in the case where the photoresistlayer 118 is set to cover the second dummy dense line pattern 114 ₂,when the distance dl from the edge 118 a of the photoresist layer 118 tothe dummy dense line pattern 114 ₁ that is closest to the edge 118 a isless than a distance d3 between the first dummy dense line pattern 114 ₁and the second dummy dense line pattern 114 ₂, it is determined that thelanding position of the photoresist layer 118 is incorrect. Even if thedetermination result is positive, it is necessary to measure the width wof the connection portion 116 by the CD-SEM. If a measured value cannotbe obtained, it is determined that the landing position of thephotoresist layer 118 is incorrect, and so on.

In a case where the landing position of the photoresist layer 118 iscorrect, the photoresist layer 118, the dummy dense line patterns 114,and the dense line patterns 112 of FIG. 8A are used as a mask to carryout a series of processes as described in the second embodiment, and asemiconductor device 900 as shown in FIG. 9 may be formed. Thesemiconductor device 900 includes dense line structures 902 and atruncating circuit 904. This embodiment is different from the secondembodiment in that the truncating circuit 904 is linear like the denseline structures 902, and that multiple extensions 908 adjacent to atruncating portion 906 and extending toward the peripheral region 10 bare further provided. A line width of the truncating circuit 904 may beequal to or not equal to a line width of the dense line structures 902.The other content omitted here may be understood with reference to thesecond embodiment.

In addition to determining whether the landing position of thephotoresist layer is correct, with reference to FIGS. 10A and 10B, thefirst embodiment may also be applied to detection of critical dimension(CD) and overlap.

FIG. 10A shows a reduced view of FIG. 6A, where the cell region 10 a isbetween the peripheral regions 10 b, and the interface between the cellregion 10 a and the peripheral regions 10 b may be observed from theconnection portion 116. Two distances d1 a and d1 b between oppositesides (that is, from the edge 118 a to the closest dummy dense linepatterns 114) of the photoresist layer 118 obtained by aphotolithography process may be used to estimate a CD value of thephotoresist layer 118. If the two distances d1 a and d1 b are smallerthan a set value, it means that the cell region 10 a will become smallerafter this photolithography process, and parameters of the subsequentphotolithography process should be adjusted. If the two distances d1 aand d1 b are greater than the set value, it means that the cell region10 a will become larger after this photolithography process, andparameters of the subsequent photolithography process should also beadjusted.

FIG. 10B is the same as FIG. 10A except for the landing position of thephotoresist layer 118. The distance d1 a and the distance d1 b areobviously different. Therefore, an overlap amount may be measured from adifference between the distances d1 a and d1 b between opposite sides toverify whether the overlap between the layers is correct.

In summary, in the disclosure, by marking the interface between the cellregion and the peripheral region with the dummy dense line patternincluding at least one connection portion, the boundary between the cellregion and the peripheral region can be directly determined without theneed for performing additional optical proximity correction (OPC).According to the distance from the edge of the photoresist layer to theclosest dummy dense line pattern and the width of the connectionportion, it is possible to online recognize whether the landing positionof the photoresist layer is correct. In addition, the above recognitionmethod may also be applied to detection of CD and overlap.

What is claimed is:
 1. A recognition method for a photolithographyprocess, comprising: forming a mask layer on a semiconductor substrate,the semiconductor substrate comprising a cell region and a peripheralregion; patterning the mask layer to form a plurality of dense linepatterns in the cell region, and to form a plurality of dummy dense linepatterns in an interface region between the cell region and theperipheral region, wherein at least one connection portion is providedbetween a first and a third of the plurality of dummy dense linepatterns, and a second of the plurality of dummy dense line patterns isdiscontinuous at the at least one connection portion and is separatedfrom the at least one connection portion; forming on the semiconductorsubstrate a photoresist layer covering the peripheral region; anddetermining whether a landing position of the photoresist layer iscorrect according to a distance from an edge of the photoresist layer toa closest one of the plurality of dummy dense line patterns and a widthof the at least one connection portion.
 2. The recognition method for aphotolithography process according to claim 1, wherein in a case wherethe photoresist layer is set to cover the first of the plurality ofdummy dense line patterns, the landing position of the photoresist layeris determined to be incorrect in response to the distance from the edgeof the photoresist layer to the closest one of the plurality of dummydense line patterns being smaller than a distance between the first andthe second of the plurality of dummy dense line patterns.
 3. Therecognition method for photolithography process according to claim 1,wherein in a case where the photoresist layer is set to cover the firstof the plurality of dummy dense line patterns, the landing position ofthe photoresist layer is determined to be incorrect in response to ameasured value being unable to be obtained by a critical dimensionscanning electron microscope (CD-SEM).
 4. The recognition method for aphotolithography process according to claim 1, wherein in a case wherethe photoresist layer is set to cover the second of the plurality ofdummy dense line patterns, the landing position of the photoresist layeris determined to be incorrect in response to the distance from the edgeof the photoresist layer to the closest one of the plurality of dummydense line patterns being smaller than a distance between the first andthe second of the plurality of dummy dense line patterns.
 5. Therecognition method for a photolithography process according to claim 1,wherein in a case where the photoresist layer is set to cover the secondof the plurality of dummy dense line patterns, the landing position ofthe photoresist layer is determined to be incorrect in response to ameasured value being unable to be obtained by a CD-SEM.
 6. Therecognition method for a photolithography process according to claim 1,further comprising estimating a critical dimension (CD) value of thephotoresist layer according to a value of the distance between oppositesides.
 7. The recognition method for a photolithography processaccording to claim 1, further comprising measuring an overlap amountaccording to a difference in the distance between opposite sides.
 8. Therecognition method for a photolithography process according to claim 1,wherein the mask layer is formed using a self-aligned double patterning(SADP) process.
 9. A semiconductor device, comprising: a semiconductorsubstrate comprising a cell region and a peripheral region; a pluralityof dense line structures formed in the semiconductor substrate or on thesemiconductor substrate, wherein the plurality of dense line structuresare obtained by carrying out an etching process or a deposition processusing the plurality of dense line patterns in the recognition methodaccording to claim 1 as a mask, and the plurality of dense linestructures and the plurality of dense line patterns are complementarypatterns; and a truncating circuit disposed on an interface between theplurality of dense line structures and the peripheral region, whereinthe truncating circuit is obtained by carrying out an etching process ora deposition process using the photoresist layer and the plurality ofdummy dense line patterns in the recognition method according to claim 1as a mask, and the truncating circuit and the first to the third of theplurality of dummy dense line patterns are complementary patterns,wherein the truncating circuit has at least one truncating portioncomplementary to the at least one connection portion of the dummy denseline patterns.
 10. The semiconductor device according to claim 9,wherein the plurality of dense line structures comprise a buried wordline, a bit line, or a shallow trench isolation structure.
 11. Thesemiconductor device according to claim 9, wherein a line width of thetruncating circuit is equal to a line width of the plurality of denseline structures.
 12. The semiconductor device according to claim 9,wherein the truncating circuit comprises a plurality of extensionsadjacent to the at least one truncating portion and extending toward theperipheral region.
 13. The semiconductor device according to claim 9,wherein the truncating circuit is constituted by a plurality of closedrings, and the at least one truncating portion is disposed between twoof the plurality of closed rings.
 14. The semiconductor device accordingto claim 13, wherein a line width of each of the plurality of closedrings is equal to a line width of the plurality of dense linestructures.